Index: sys/arch/sparc/dev/audioamd.c =================================================================== RCS file: /cvsroot/syssrc/sys/arch/sparc/dev/audioamd.c,v retrieving revision 1.13 diff -u -r1.13 audioamd.c --- sys/arch/sparc/dev/audioamd.c 2002/10/15 13:49:52 1.13 +++ sys/arch/sparc/dev/audioamd.c 2002/12/05 19:29:05 @@ -64,20 +64,11 @@ /* interrupt interfaces */ #ifdef AUDIO_C_HANDLER int am7930hwintr __P((void *)); -#if defined(SUN4M) -#define AUDIO_SET_SWINTR do { \ - if (CPU_ISSUN4M) \ - raise(0, 4); \ - else \ - ienab_bis(IE_L4); \ -} while(0); +#define AUDIO_SET_SWINTR softintr_schedule(sc->sc_sicookie) #else -#define AUDIO_SET_SWINTR ienab_bis(IE_L4) -#endif /* defined(SUN4M) */ -#else struct auio *auiop; #endif /* AUDIO_C_HANDLER */ -int am7930swintr __P((void *)); +void am7930swintr __P((void *)); /* * interrupt-handler status @@ -102,6 +93,8 @@ /* sc_au is special in that the hardware interrupt handler uses it */ struct auio sc_au; /* recv and xmit buffers, etc */ #define sc_intrcnt sc_au.au_intrcnt /* statistics */ + + void *sc_sicookie; /* softintr(9) cookie */ }; void audioamd_mainbus_attach __P((struct device *, @@ -306,8 +299,15 @@ int pri; { - printf(" softpri %d\n", PIL_AUSOFT); + sc->sc_sicookie = softintr_establish(IPL_SOFTAUDIO, am7930swintr, sc); + if (sc->sc_sicookie == NULL) { + printf("\n%s: cannot establish software interrupt\n", + sc->sc_am7930.sc_dev.dv_xname); + return; + } + printf(" softpri %d\n", softintr_priority(sc->sc_sicookie)); + /* * Set up glue for MI code early; we use some of it here. */ @@ -324,9 +324,6 @@ (void)bus_intr_establish(sc->sc_bt, pri, IPL_AUDIO, 0, am7930hwintr, sc); #endif - (void)bus_intr_establish(sc->sc_bt, PIL_AUSOFT, IPL_AUDIO, - BUS_INTR_ESTABLISH_SOFTINTR, - am7930swintr, sc); evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, NULL, sc->sc_am7930.sc_dev.dv_xname, "intr"); @@ -466,13 +463,13 @@ } #endif /* AUDIO_C_HANDLER */ -int +void am7930swintr(sc0) void *sc0; { struct audioamd_softc *sc = sc0; struct auio *au; - int s, ret = 0; + int s; DPRINTFN(1, ("audiointr: sc=%p\n", sc);); @@ -480,17 +477,14 @@ s = splaudio(); if (au->au_rdata > au->au_rend && sc->sc_rintr != NULL) { splx(s); - ret = 1; (*sc->sc_rintr)(sc->sc_rarg); s = splaudio(); } if (au->au_pdata > au->au_pend && sc->sc_pintr != NULL) { splx(s); - ret = 1; (*sc->sc_pintr)(sc->sc_parg); } else splx(s); - return (ret); } Index: sys/arch/sparc/dev/fd.c =================================================================== RCS file: /cvsroot/syssrc/sys/arch/sparc/dev/fd.c,v retrieving revision 1.96 diff -u -r1.96 fd.c --- sys/arch/sparc/dev/fd.c 2002/11/01 11:31:53 1.96 +++ sys/arch/sparc/dev/fd.c 2002/12/05 19:29:06 @@ -174,6 +174,8 @@ #define sc_nstat sc_io.fdcio_nstat #define sc_status sc_io.fdcio_status #define sc_intrcnt sc_io.fdcio_intrcnt + + void *sc_sicookie; /* softintr(9) cookie */ }; extern struct fdcio *fdciop; /* I/O descriptor used in fdintr.s */ @@ -302,7 +304,7 @@ void fdcpseudointr __P((void *arg)); int fdc_c_hwintr __P((void *)); void fdchwintr __P((void)); -int fdcswintr __P((void *)); +void fdcswintr __P((void *)); int fdcstate __P((struct fdc_softc *)); void fdcretry __P((struct fdc_softc *fdc)); void fdfinish __P((struct fd_softc *fd, struct buf *bp)); @@ -317,23 +319,8 @@ bus_size_t, bus_space_handle_t)); - -#if PIL_FDSOFT == 4 -#define IE_FDSOFT IE_L4 -#else -#error 4 -#endif -#if defined(SUN4M) -#define FD_SET_SWINTR do { \ - if (CPU_ISSUN4M) \ - raise(0, PIL_FDSOFT); \ - else \ - ienab_bis(IE_L4); \ -} while(0) -#else -#define FD_SET_SWINTR ienab_bis(IE_FDSOFT) -#endif /* defined(SUN4M) */ +#define FD_SET_SWINTR softintr_schedule(fdc->sc_sicookie) #define OBP_FDNAME (CPU_ISSUN4M ? "SUNW,fdtwo" : "fd") @@ -624,7 +611,16 @@ code = '2'; } - printf(" softpri %d: chip 8207%c\n", PIL_FDSOFT, code); + fdc->sc_sicookie = softintr_establish(IPL_SOFTFLOPPY, + fdcswintr, fdc); + if (fdc->sc_sicookie == NULL) { + printf("\n%s: cannot register soft interrupt handler\n", + fdc->sc_dev.dv_xname); + return (-1); + } + + printf(" softpri %d: chip 8207%c\n", + softintr_priority(fdc->sc_sicookie), code); /* * Configure controller; enable FIFO, Implied seek, no POLL mode?. @@ -633,6 +629,7 @@ fdc->sc_cfg = CFG_EIS|/*CFG_EFIFO|*/CFG_POLL|(8 & CFG_THRHLD_MASK); if (fdconf(fdc) != 0) { printf("%s: no drives attached\n", fdc->sc_dev.dv_xname); + softintr_disestablish(fdc->sc_sicookie); return (-1); } @@ -647,18 +644,11 @@ fdc_c_hwintr, fdc) == NULL) { printf("%s: cannot register interrupt handler\n", fdc->sc_dev.dv_xname); + softintr_disestablish(fdc->sc_sicookie); return (-1); } } - if (bus_intr_establish(fdc->sc_bustag, PIL_FDSOFT, IPL_BIO, - BUS_INTR_ESTABLISH_SOFTINTR, - fdcswintr, fdc) == NULL) { - printf("%s: cannot register interrupt handler\n", - fdc->sc_dev.dv_xname); - return (-1); - } - evcnt_attach_dynamic(&fdc->sc_intrcnt, EVCNT_TYPE_INTR, NULL, fdc->sc_dev.dv_xname, "intr"); @@ -1375,7 +1365,7 @@ return (1); } -int +void fdcswintr(arg) void *arg; { @@ -1384,7 +1374,7 @@ if (fdc->sc_istatus == FDC_ISTATUS_NONE) /* This (software) interrupt is not for us */ - return (0); + return; switch (fdc->sc_istatus) { case FDC_ISTATUS_ERROR: @@ -1398,7 +1388,7 @@ s = splbio(); fdcstate(fdc); splx(s); - return (1); + return; } int Index: sys/arch/sparc/dev/sbus.c =================================================================== RCS file: /cvsroot/syssrc/sys/arch/sparc/dev/sbus.c,v retrieving revision 1.52 diff -u -r1.52 sbus.c --- sys/arch/sparc/dev/sbus.c 2002/10/02 16:02:16 1.52 +++ sys/arch/sparc/dev/sbus.c 2002/12/05 19:29:06 @@ -682,9 +682,7 @@ /* * Translate Sbus interrupt priority to CPU interrupt level */ - if ((flags & BUS_INTR_ESTABLISH_SOFTINTR) != 0) - pil = pri; - else if ((pri & SBUS_INTR_COMPAT) != 0) + if ((pri & SBUS_INTR_COMPAT) != 0) pil = pri & ~SBUS_INTR_COMPAT; else pil = sc->sc_intr2ipl[pri]; Index: sys/arch/sparc/dev/zs.c =================================================================== RCS file: /cvsroot/syssrc/sys/arch/sparc/dev/zs.c,v retrieving revision 1.92 diff -u -r1.92 zs.c --- sys/arch/sparc/dev/zs.c 2002/10/09 08:56:25 1.92 +++ sys/arch/sparc/dev/zs.c 2002/12/05 19:29:06 @@ -96,19 +96,6 @@ */ #define PCLK (9600 * 512) /* PCLK pin input clock rate */ -/* - * Select software interrupt bit based on TTY ipl. - */ -#if PIL_TTY == 1 -# define IE_ZSSOFT IE_L1 -#elif PIL_TTY == 4 -# define IE_ZSSOFT IE_L4 -#elif PIL_TTY == 6 -# define IE_ZSSOFT IE_L6 -#else -# error "no suitable software interrupt bit" -#endif - #define ZS_DELAY() (CPU_ISSUN4C ? (0) : delay(2)) /* The layout of this is hardware-dependent (padding, order). */ @@ -192,9 +179,12 @@ extern struct cfdriver zs_cd; +/* softintr(9) cookie, shared by all instances of this driver */ +static void *zs_sicookie; + /* Interrupt handlers. */ static int zshard __P((void *)); -static int zssoft __P((void *)); +static void zssoft __P((void *)); static int zs_get_speed __P((struct zs_chanstate *)); @@ -434,8 +424,17 @@ printf("configuration incomplete\n"); return; } + + if (!didintr) { + zs_sicookie = softintr_establish(IPL_SOFTSERIAL, zssoft, NULL); + if (zs_sicookie == NULL) { + printf("\n%s: cannot establish soft int handler\n", + zsc->zsc_dev.dv_xname); + return; + } + } - printf(" softpri %d\n", PIL_TTY); + printf(" softpri %d\n", softintr_priority(zs_sicookie)); /* * Initialize software state for each channel. @@ -520,10 +519,6 @@ prevpri = pri; bus_intr_establish(zsc->zsc_bustag, pri, IPL_SERIAL, 0, zshard, NULL); - bus_intr_establish(zsc->zsc_bustag, PIL_TTY, - IPL_SOFTSERIAL, - BUS_INTR_ESTABLISH_SOFTINTR, - zssoft, NULL); } else if (pri != prevpri) panic("broken zs interrupt scheme"); @@ -606,13 +601,8 @@ /* We are at splzs here, so no need to lock. */ if (softreq && (zssoftpending == 0)) { - zssoftpending = IE_ZSSOFT; -#if defined(SUN4M) - if (CPU_ISSUN4M) - raise(0, PIL_TTY); - else -#endif - ienab_bis(IE_ZSSOFT); + zssoftpending = 1; + softintr_schedule(zs_sicookie); } return (rval); } @@ -620,7 +610,7 @@ /* * Similar scheme as for zshard (look at all of them) */ -static int +static void zssoft(arg) void *arg; { @@ -629,7 +619,7 @@ /* This is not the only ISR on this IPL. */ if (zssoftpending == 0) - return (0); + return; /* * The soft intr. bit will be set by zshard only if @@ -649,7 +639,6 @@ (void)zsc_intr_soft(zsc); } splx(s); - return (1); } Index: sys/arch/sparc/include/bus.h =================================================================== RCS file: /cvsroot/syssrc/sys/arch/sparc/include/bus.h,v retrieving revision 1.33 diff -u -r1.33 bus.h --- sys/arch/sparc/include/bus.h 2002/08/25 17:55:00 1.33 +++ sys/arch/sparc/include/bus.h 2002/12/05 19:29:07 @@ -320,7 +320,6 @@ /* flags for intr_establish() */ #define BUS_INTR_ESTABLISH_FASTTRAP 1 -#define BUS_INTR_ESTABLISH_SOFTINTR 2 /* flags for bus_space_barrier() */ #define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */ Index: sys/arch/sparc/include/cpu.h =================================================================== RCS file: /cvsroot/syssrc/sys/arch/sparc/include/cpu.h,v retrieving revision 1.51 diff -u -r1.51 cpu.h --- sys/arch/sparc/include/cpu.h 2002/11/28 15:29:53 1.51 +++ sys/arch/sparc/include/cpu.h 2002/12/05 19:29:07 @@ -125,17 +125,6 @@ #define CLKF_INTR(framep) ((framep)->fp < (u_int)eintstack) #endif -#if defined(SUN4M) -extern void raise __P((int, int)); -#if !(defined(SUN4) || defined(SUN4C)) -#define setsoftint() raise(0,1) -#else /* both defined */ -#define setsoftint() (cputyp == CPU_SUN4M ? raise(0,1) : ienab_bis(IE_L1)) -#endif /* !4,!4c */ -#else /* 4m not defined */ -#define setsoftint() ienab_bis(IE_L1) -#endif /* SUN4M */ - void softintr_init __P((void)); void *softnet_cookie; Index: sys/arch/sparc/include/intr.h =================================================================== RCS file: /cvsroot/syssrc/sys/arch/sparc/include/intr.h,v retrieving revision 1.3 diff -u -r1.3 intr.h --- sys/arch/sparc/include/intr.h 2001/09/27 02:05:42 1.3 +++ sys/arch/sparc/include/intr.h 2002/12/05 19:29:07 @@ -42,7 +42,9 @@ #define IPL_SOFTNET 1 /* protocol stack */ #define IPL_BIO 2 /* block I/O */ #define IPL_NET 3 /* network */ -#define IPL_SOFTSERIAL 4 /* serial */ +#define IPL_SOFTAUDIO 4 /* soft audio */ +#define IPL_SOFTFLOPPY 4 /* soft floppy */ +#define IPL_SOFTSERIAL 5 /* serial */ #define IPL_TTY 5 /* terminal */ #define IPL_IMP 6 /* memory allocation */ #define IPL_AUDIO 7 /* audio */ @@ -50,10 +52,37 @@ #define IPL_SERIAL 9 /* serial */ #define IPL_HIGH 10 /* everything */ +#ifdef _KERNEL + +#if !defined(_LKM) && defined(_KERNEL_OPT) +#include "opt_sparc_arch.h" +#endif + void * softintr_establish __P((int level, void (*fun)(void *), void *arg)); void softintr_disestablish __P((void *cookie)); + +int +softintr_priority __P((void *cookie)); + +/* + * NB that softintr_schedule() casts the cookie to an int *. + * This is to get the sic_pilreq member of the softintr_cookie + * structure, which is otherwise internal to intr.c. + */ +#if defined(SUN4M) +extern void raise __P((int, int)); +#if !(defined(SUN4) || defined(SUN4C)) +#define softintr_schedule(cookie) raise(0, *((int *) (cookie))) +#else /* both defined */ +#define softintr_schedule(cookie) (cputyp == CPU_SUN4M ? \ + raise(0, *((int *) (cookie))) : \ + ienab_bis(*((int *) (cookie)))) +#endif /* !4,!4c */ +#else /* 4m not defined */ +#define softintr_schedule(cookie) ienab_bis(*((int *) (cookie))) +#endif /* SUN4M */ -#define softintr_schedule(cookie) setsoftint() +#endif /* _KERNEL */ Index: sys/arch/sparc/sparc/intr.c =================================================================== RCS file: /cvsroot/syssrc/sys/arch/sparc/sparc/intr.c,v retrieving revision 1.60 diff -u -r1.60 intr.c --- sys/arch/sparc/sparc/intr.c 2002/09/27 15:36:47 1.60 +++ sys/arch/sparc/sparc/intr.c 2002/12/05 19:29:07 @@ -74,6 +74,20 @@ void *softnet_cookie; +/* + * This is a softintr cookie. NB that sic_pilreq MUST be the + * first element in the struct, because the softintr_schedule() + * macro in intr.h casts cookies to int * to get it. On a + * sun4m, sic_pilreq is an actual processor interrupt level that + * is passed to raise(), and on a sun4 or sun4c sic_pilreq is a + * bit to set in the interrupt enable register with ienab_bis(). + */ +struct softintr_cookie { + int sic_pilreq; /* MUST be first! */ + int sic_pil; + struct intrhand sic_hand; +}; + void strayintr __P((struct clockframe *)); #ifdef DIAGNOSTIC void bogusintr __P((struct clockframe *)); @@ -551,15 +565,80 @@ void (*fun) __P((void *)); void *arg; { + struct softintr_cookie *sic; struct intrhand *ih; + int pil; + int pilreq; + + /* + * Turn the IPL_ identifier into a processor + * interrupt level. + */ + if (level == IPL_SOFTCLOCK) + pil = 1; /* XXX needs a PIL_ macro */ + else if (level == IPL_SOFTNET) + pil = 1; /* XXX needs a PIL_ macro */ + else if (level == IPL_SOFTAUDIO) + pil = PIL_AUSOFT; + else if (level == IPL_SOFTFLOPPY) + pil = PIL_FDSOFT; + else if (level == IPL_SOFTSERIAL) + pil = PIL_TTY; + else { +#ifdef DIAGNOSTIC + printf("softintr_establish: bad soft ipl %d\n", level); +#endif + return (NULL); + } - ih = malloc(sizeof(*ih), M_DEVBUF, 0); - bzero(ih, sizeof(*ih)); + /* + * On a sun4m the processor interrupt level is stored + * in the softintr cookie to be passed to raise(). + * On a sun4 or sun4c the appropriate bit to set + * in the interrupt enable register is stored in + * the softintr cookie to be passed to ienab_bis(). + */ + if (CPU_ISSUN4M) + pilreq = pil; + else if (CPU_ISSUN4 || CPU_ISSUN4C) { + switch (pil) { + case 1: pilreq = IE_L1; break; + case 4: pilreq = IE_L4; break; + case 6: pilreq = IE_L6; break; + default: +#ifdef DIAGNOSTIC + printf("softintr_establish: bad soft pil %d\n", pil); +#endif + return (NULL); + } + } + else + panic("softintr_establish"); + + sic = malloc(sizeof(*sic), M_DEVBUF, 0); + bzero(sic, sizeof(*sic)); + sic->sic_pil = pil; + sic->sic_pilreq = pilreq; + ih = &sic->sic_hand; ih->ih_fun = (int (*) __P((void *)))fun; ih->ih_arg = arg; ih->ih_next = 0; - intr_establish(1, ih); - return (void *)ih; + intr_establish(pil, ih); + return (void *)sic; +} + +/* + * softintr_priority(): MI interface. returns the CPU priority level + * of the specified software interrupt. shouldn't be treated as a + * real CPU priority level in any way except for use in printf()s in + * device attach routines. + */ +int +softintr_priority(cookie) + void *cookie; +{ + struct softintr_cookie *sic = cookie; + return (sic->sic_pil); } /* @@ -570,8 +649,9 @@ softintr_disestablish(cookie) void *cookie; { + struct softintr_cookie *sic = cookie; - intr_disestablish(1, cookie); + intr_disestablish(sic->sic_pil, cookie); free(cookie, M_DEVBUF); } Index: sys/arch/sparc64/dev/psycho.c =================================================================== RCS file: /cvsroot/syssrc/sys/arch/sparc64/dev/psycho.c,v retrieving revision 1.55 diff -u -r1.55 psycho.c --- sys/arch/sparc64/dev/psycho.c 2002/10/02 16:02:19 1.55 +++ sys/arch/sparc64/dev/psycho.c 2002/12/05 19:29:08 @@ -1042,48 +1042,45 @@ level = 2; } - if ((flags & BUS_INTR_ESTABLISH_SOFTINTR) == 0) { + DPRINTF(PDB_INTR, ("\npsycho: intr %lx: %p\nHunting for IRQ...\n", + (long)ino, intrlev[ino])); - DPRINTF(PDB_INTR, ("\npsycho: intr %lx: %p\nHunting for IRQ...\n", - (long)ino, intrlev[ino])); - - /* Hunt thru obio first */ - for (intrmapptr = &sc->sc_regs->scsi_int_map, - intrclrptr = &sc->sc_regs->scsi_clr_int; - intrmapptr < &sc->sc_regs->ffb0_int_map; - intrmapptr++, intrclrptr++) { - if (INTINO(*intrmapptr) == ino) - goto found; - } + /* Hunt thru obio first */ + for (intrmapptr = &sc->sc_regs->scsi_int_map, + intrclrptr = &sc->sc_regs->scsi_clr_int; + intrmapptr < &sc->sc_regs->ffb0_int_map; + intrmapptr++, intrclrptr++) { + if (INTINO(*intrmapptr) == ino) + goto found; + } - /* Now do PCI interrupts */ - for (intrmapptr = &sc->sc_regs->pcia_slot0_int, - intrclrptr = &sc->sc_regs->pcia0_clr_int[0]; - intrmapptr <= &sc->sc_regs->pcib_slot3_int; - intrmapptr++, intrclrptr += 4) { - if (((*intrmapptr ^ vec) & 0x3c) == 0) { - intrclrptr += vec & 0x3; - goto found; - } + /* Now do PCI interrupts */ + for (intrmapptr = &sc->sc_regs->pcia_slot0_int, + intrclrptr = &sc->sc_regs->pcia0_clr_int[0]; + intrmapptr <= &sc->sc_regs->pcib_slot3_int; + intrmapptr++, intrclrptr += 4) { + if (((*intrmapptr ^ vec) & 0x3c) == 0) { + intrclrptr += vec & 0x3; + goto found; } + } - /* Finally check the two FFB slots */ - intrclrptr = NULL; /* XXX? */ - for (intrmapptr = &sc->sc_regs->ffb0_int_map; - intrmapptr <= &sc->sc_regs->ffb1_int_map; - intrmapptr++) { - if (INTVEC(*intrmapptr) == ino) - goto found; - } + /* Finally check the two FFB slots */ + intrclrptr = NULL; /* XXX? */ + for (intrmapptr = &sc->sc_regs->ffb0_int_map; + intrmapptr <= &sc->sc_regs->ffb1_int_map; + intrmapptr++) { + if (INTVEC(*intrmapptr) == ino) + goto found; + } - printf("Cannot find interrupt vector %lx\n", vec); - return (NULL); + printf("Cannot find interrupt vector %lx\n", vec); + return (NULL); - found: - /* Register the map and clear intr registers */ - ih->ih_map = intrmapptr; - ih->ih_clr = intrclrptr; - } +found: + /* Register the map and clear intr registers */ + ih->ih_map = intrmapptr; + ih->ih_clr = intrclrptr; #ifdef NOT_DEBUG if (psycho_debug & PDB_INTR) { long i; Index: sys/arch/sparc64/dev/sbus.c =================================================================== RCS file: /cvsroot/syssrc/sys/arch/sparc64/dev/sbus.c,v retrieving revision 1.55 diff -u -r1.55 sbus.c --- sys/arch/sparc64/dev/sbus.c 2002/10/02 16:02:19 1.55 +++ sys/arch/sparc64/dev/sbus.c 2002/12/05 19:29:08 @@ -621,9 +621,7 @@ if (ih == NULL) return (NULL); - if ((flags & BUS_INTR_ESTABLISH_SOFTINTR) != 0) - ipl = vec; - else if ((vec & SBUS_INTR_COMPAT) != 0) + if ((vec & SBUS_INTR_COMPAT) != 0) ipl = vec & ~SBUS_INTR_COMPAT; else { /* Decode and remove IPL */ Index: sys/arch/sparc64/include/bus.h =================================================================== RCS file: /cvsroot/syssrc/sys/arch/sparc64/include/bus.h,v retrieving revision 1.39 diff -u -r1.39 bus.h --- sys/arch/sparc64/include/bus.h 2002/03/21 00:43:42 1.39 +++ sys/arch/sparc64/include/bus.h 2002/12/05 19:29:09 @@ -339,7 +339,6 @@ /* flags for intr_establish() */ #define BUS_INTR_ESTABLISH_FASTTRAP 1 -#define BUS_INTR_ESTABLISH_SOFTINTR 2 /* flags for bus_space_barrier() */ #define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */ Index: sys/arch/sparc64/include/intr.h =================================================================== RCS file: /cvsroot/syssrc/sys/arch/sparc64/include/intr.h,v retrieving revision 1.8 diff -u -r1.8 intr.h --- sys/arch/sparc64/include/intr.h 2001/01/14 23:50:30 1.8 +++ sys/arch/sparc64/include/intr.h 2002/12/05 19:29:09 @@ -36,7 +36,11 @@ * POSSIBILITY OF SUCH DAMAGE. */ -/* XXX - arbitrary numbers; no interpretation is defined yet */ +/* + * XXX - at least the softintr(9) implementation assumes that + * the IPL_SOFT* identifiers correspond to real processor interrupt + * levels, other things may assume this too? + */ #define IPL_NONE 0 /* nothing */ #define IPL_SOFTINT 1 /* softint */ #define IPL_SOFTCLOCK 1 /* timeouts */ @@ -55,6 +59,9 @@ void * softintr_establish __P((int level, void (*fun)(void *), void *arg)); + +int +softintr_priority __P((void *cookie)); void softintr_disestablish __P((void *cookie)); Index: sys/arch/sparc64/sparc64/intr.c =================================================================== RCS file: /cvsroot/syssrc/sys/arch/sparc64/sparc64/intr.c,v retrieving revision 1.43 diff -u -r1.43 intr.c --- sys/arch/sparc64/sparc64/intr.c 2002/06/07 19:31:04 1.43 +++ sys/arch/sparc64/sparc64/intr.c 2002/12/05 19:29:09 @@ -325,6 +325,14 @@ return (void *)ih; } +int +softintr_priority(cookie) + void *cookie; +{ + struct intrhand *ih = (struct intrhand *)cookie; + return ih->ih_pil; +} + void softintr_disestablish(cookie) void *cookie; Index: sys/dev/sbus/magma.c =================================================================== RCS file: /cvsroot/syssrc/sys/dev/sbus/magma.c,v retrieving revision 1.21 diff -u -r1.21 magma.c --- sys/dev/sbus/magma.c 2002/10/23 09:13:42 1.21 +++ sys/dev/sbus/magma.c 2002/12/05 19:29:10 @@ -73,19 +73,6 @@ #include #include -/* - * Select tty soft interrupt bit based on TTY ipl. (stole from zs.c) - */ -#if PIL_TTY == 1 -# define IE_MSOFT IE_L1 -#elif PIL_TTY == 4 -# define IE_MSOFT IE_L4 -#elif PIL_TTY == 6 -# define IE_MSOFT IE_L6 -#else -# error "no suitable software interrupt bit" -#endif - /* supported cards * * The table below lists the cards that this driver is likely to @@ -402,7 +389,15 @@ } dprintf((" addr %p", sc)); - printf(" softpri %d: %s\n", PIL_TTY, card->mb_realname); + + sc->ms_sicookie = softintr_establish(IPL_SOFTSERIAL, magma_soft, sc); + if (sc->ms_sicookie == NULL) { + printf("\n%s: cannot establish soft interrupt handler\n", + self->dv_xname); + return; + } + printf(" softpri %d: %s\n", + softintr_priority(sc->ms_sicookie), card->mb_realname); sc->ms_board = card; sc->ms_ncd1400 = card->mb_ncd1400; @@ -497,14 +492,13 @@ /* * Establish the interrupt handlers. */ - if (sa->sa_nintr == 0) + if (sa->sa_nintr == 0) { + softintr_disestablish(sc->ms_sicookie); return; /* No interrupts to service!? */ + } (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_TTY, 0, magma_hard, sc); - (void)bus_intr_establish(sa->sa_bustag, PIL_TTY, IPL_SOFTSERIAL, - BUS_INTR_ESTABLISH_SOFTINTR, - magma_soft, sc); evcnt_attach_dynamic(&sc->ms_intrcnt, EVCNT_TYPE_INTR, NULL, sc->ms_dev.dv_xname, "intr"); } @@ -726,12 +720,7 @@ */ if( needsoftint ) { /* trigger the soft interrupt */ -#if defined(SUN4M) - if( CPU_ISSUN4M ) - raise(0, PIL_TTY); - else -#endif - ienab_bis(IE_MSOFT); + softintr_schedule(sc->ms_sicookie); } return(serviced); @@ -744,7 +733,7 @@ * * runs at spltty() */ -int +void magma_soft(arg) void *arg; { @@ -825,7 +814,7 @@ * Check the bpp ports (if any) to see what needs doing */ if (mbpp == NULL) - return (serviced); + return; for( port = 0 ; port < mbpp->ms_nports ; port++ ) { struct mbpp_port *mp = &mbpp->ms_port[port]; @@ -845,7 +834,7 @@ } /* for(each mbpp...) */ - return(serviced); + return; } /************************************************************************ Index: sys/dev/sbus/magmareg.h =================================================================== RCS file: /cvsroot/syssrc/sys/dev/sbus/magmareg.h,v retrieving revision 1.5 diff -u -r1.5 magmareg.h --- sys/dev/sbus/magmareg.h 2002/09/06 13:23:27 1.5 +++ sys/dev/sbus/magmareg.h 2002/12/05 19:29:10 @@ -123,6 +123,7 @@ struct mtty_softc *ms_mtty; struct mbpp_softc *ms_mbpp; + void *ms_sicookie; /* softintr(9) cookie */ }; #define MTTY_RBUF_SIZE (2 * 512) @@ -210,7 +211,7 @@ int magma_match __P((struct device *, struct cfdata *, void *)); void magma_attach __P((struct device *, struct device *, void *)); int magma_hard __P((void *)); -int magma_soft __P((void *)); +void magma_soft __P((void *)); int mtty_match __P((struct device *, struct cfdata *, void *)); void mtty_attach __P((struct device *, struct device *, void *));